The present invention relates to integrated circuits and, more particularly, to wafer testing integrated circuits.
Electronic circuits are routinely fabricated on semiconductor wafers to form integrated circuits (ICs). Typically, each IC contains complex circuitry (referred to herein as xe2x80x9cwafer logicxe2x80x9d) which needs to be tested to ensure that it functions as intended. Prior to performing a relatively expensive packaging procedure, in which the IC is encapsulate in a protective package, the IC is xe2x80x9cwafer testedxe2x80x9dand defective ICs are discarded, thereby realizing significant cost savings. Unfortunately, due to the architecture of existing ICs and the available wafer testing equipment to test them, some ICs (e.g., Flip-Chip ICs) are unable to be fully tested during wafer testing. Flip-Chip ICs contain semiconductor wafers with a large number of bonding pads. The semiconductor wafers are inverted (xe2x80x9cflippedxe2x80x9d) prior to packaging to facilitate connections between the bonding pads and leads of the package. The inability to fully wafer test these ICs results in defective ICs being packaged, and an associated increase in production costs. Accordingly, improved methods and apparatuses which enable ICs such as Flip-Chip ICs to be tested fully during wafer test are useful.
FIG. 1 depicts a typical IC 10 prior to packaging. Older ICs have buffer areas positioned solely along the perimeter of the IC 10. The outside row buffer area 14 is typical of these outside row buffer areas. For example, there are 10 outside row buffer areas 14 along the left hand perimeter of the IC 10. The IC 10 is a semiconductor wafer which has logic dispersed throughout the entire wafer. For descriptive purposes, the logic dispersed through out the IC 10 is referred to as wafer logic 12.
Each outside row buffer area 14 includes an outside row bonding pad 14A which is electrically connected to wafer logic 12 within the IC 10 through an outside row buffer 14B. The outside row buffers 14B are fabricated within the IC 10 and, therefore, are not visible (represented through the use of dashed lines). As long as all of the buffer areas 14 are positioned along the perimeter of the IC 10, the wafer logic 12 of the IC 10 can be wafer tested filly prior to packaging by use of conventional mechanical probes (representatively shown by probe element 18 in FIG. 1) which contact the outside row bonding pads 14A. The probe element 18 temporarily contacts the bonding pads 14A during testing to supply and interpret testing signals of the IC 10. A conventional cantilever test probe is an example of a probe element that may be used for wafer testing ICs.
Typically, the outside row buffer 14B comprises an input stage which permits signals impressed at the outside row bonding pad 14A to reach the wafer logic 12, an output stage which permits signals from the wafer logic 12 to reach the outside row bonding pad 14A, or an input stage and output stage to permit two-way communication between the outside row bonding pad 14A and the wafer logic 12.
In newer ICs, in addition to the previously described outside row buffer areas 14, inside row buffer areas are positioned in a central portion of the IC 10, as shown in FIG. 1, to establish contact with the increasingly complex circuitry of these ICs 10. The inside row buffer area 16 is typical of these inside row buffer areas. For example, there are 4 inside row buffer areas 16 along the left hand interior region of the IC 10. The inside row buffer area 16 includes an inside row bonding pad 16A electrically connected to the wafer logic 12 within the IC 10 through an inside row buffer 16B.
These modern ICs 10 may contain logic which requires that one or more inside row buffer areas 16 be contacted during testing. For example, as shown in FIG. 1, internal logic 12A accessible between inside row buffer area A and inside row buffer area Z would require that these inside row buffer areas be contacted to properly test the internal logic 12A. Also, logic within the IC 10 may be such that it is testable only between outside row buffer areas 14 and inside row buffer areas 16.
FIG. 1A depicts a cross sectional view of a Flip-Chip protective package 20 for housing the IC 10 (FIG. 1). The protective package 20 contains an array of leads, such as lead 22, which correspond to the bonding pads of the IC 10, e.g., bonding pads 14A, 16A (FIG. 1). The IC 10 depicted in FIG. 1 is only one of many possibilities for buffer area placement. For example, the buffer areas could be placed in a regular grid pattern that covers the entire chip.
In typical ICs, all of the buffer areas are physically positioned in close proximity to one another due to a relatively large number of boding pads on a relatively small piece of semiconductor material. In order to contact individual bonding pads, the probe elements 18 include very fine wires for contacting the bonding pads during testing. This makes it difficult to contact an outside row bonding pad with one probe and an inside row bonding pad behind the outside row bonding pad with another probe without the probes interfering with one another. If the probe elements contact one another during testing, a short will occur, thereby precluding the testing process.
With respect to Flip-Chips, the existing testing method is to test the portions of the wafer logic 12 accessible via the outside row buffer areas 14 during the wafer testing process (e.g., using probe elements 18) and then test the inaccessible logic (e.g., the internal logic 12A) after the IC 10 is packaged within the protective package 20 (i.e., xe2x80x9cpackage testingxe2x80x9d). During package testing, probes are attached to the leads 22 of the package 20 and testing signals are applied to test the internal logic 12A by submitting a test signal to a lead 22 attached to an appropriate inside row buffer area (e.g., buffer area A) coupled to an input of the internal logic 12A and examining the output at a lead attached to another appropriate inside row buffer area (e.g., buffer area Z) coupled to an output of the internal logic 12A. This enables the internal logic 12A to be tested, however, the IC 10 must already be packaged to use this testing method. Once the chip is placed within the package it cannot later be removed easily. Since packaging ICs is a relatively expensive portion of the cost of producing a packaged IC, it is desirable to be able to fully test all IC logic prior to packaging (i.e., during wafer testing).
Prior art attempts to fully wafer test ICs include the use of a probe known as a membrane probe. An example of a membrane probe is depicted in U.S. Pat. No. 5,990,695 to Daugherty, Jr. Membrane probes are very expensive. In addition, the use of membrane probes would require the purchase of new test equipment for wafer testing. The membrane probes and new test equipment result in additional expenses which increase production costs.
Since fully testing an IC having inside row buffer areas during wafer testing is desirable for reducing production costs, and present systems either do not allow the IC to be fully tested or are expensive, there has been a long felt need in the industry for improved ICs and methods for testing these ICs which allow them to be fully and inexpensively tested during wafer testing. The present invention solves this need among others.
The present invention discloses an IC which is fully testable during wafer test using conventional testing equipment, and a method for testing the IC. This IC and method permit the IC to be fully tested prior to packaging. Accordingly, defective ICs which appear to be functioning properly using conventional wafer testing techniques can be identified as defective before packaging using the present invention. By detecting the defective ICs prior to packaging, the IC and method of the present invention ensure that defective ICs are not packaged, thereby decreasing production costs. Also, since conventional testing equipment can be used, the present invention can be implemented inexpensively.
The wafer testable IC includes an outside row buffer area, an inside row buffer area with a bi-directional buffer coupled to logic within the IC, routing circuitry coupled between the outside row buffer area and the inside row buffer area for coupling the inside row buffer area and the outside row buffer area such that a signal can be passed between the outside row buffer area and the logic within the IC coupled to the inside row buffer area. In addition, the IC may include another outside row buffer area wherein the logic can be tested by supplying a test signal to one of the outside row buffer areas and observing a resultant signal at the other outside row buffer area.
The method of wafer testing internal logic of an IC includes supplying a test signal to a bonding pad of an outside row buffer area having an input stage, routing the test signal from the outside row buffer area to an input of the internal logic, applying the test signal to the internal logic to generate a resultant signal at an output of the internal logic, routing the resultant signal to another outside row buffer area having an output stage, and interpreting the resultant signal at a bonding pad of the other outside row buffer area.